DDR Communication on Zynq-7000
This presentation is a part of an informal talk that I gave to undergraduate students in the course EE-4218 "Reconfigurable Computing". It highlights major features of the popular xilinx reconfigurable platform zynq-7000 and established a method to talk to the DDR using available options. It is a beginner level tutorial that can be used to get familiar with FPGA design methodologies, embedded systems programming for talking to the DDR in the context of Xilinx ZC706, Zedboard and general zynq-7000 devices. I give some design suggestions on how to create finite state machines and write verilog for embedded co-processors. The presentation slides and accompanying talk are listed below. In case of any doubts please write to me. My email can be found on the bottom right. Thank you for watching. [This is a hobby video showing my own experiences]
DDR communication on the zynq-7000 (getting the message across) AXI Master burst IPIF signals and design practices Simulation results for AXI Master burst IPIF - Vivado